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Reversible Fluxon Logic With Optimized CNOT Gate Components

TitleReversible Fluxon Logic With Optimized CNOT Gate Components
Publication TypeJournal Article
Year of Publication2021
AuthorsK. D. Osborn, and W. Wustmann
JournalIEEE Trans. Appl. Supercond.
Date Publishedmar
KeywordsBallistic signaling, fluxons, power efficient, reversible computing, superconducting logic circuits

Reversible logic gates were previously implemented in superconducting circuits as adiabatic-reversible gates, which are powered with a sufficiently slow clock. In contrast, we are studying ballistic-reversible gates, where fluxons serve to both encode the information and power the gates. No power is applied to the gate apart from the energy of the input fluxons, and the two possible flux polarities represent the bit states. Undamped long Josephson junctions (LJJs), where fluxons move at practically constant speed from inertia, form the input and output channels of the gates. LJJs are connected in the gates by circuit interfaces, which are designed to allow the ballistic scattering from input to output fluxon states, using the temporary excitation of a localized mode. The duration of the resonant scattering determines the operation time of the gate, approximately a few Josephson plasma periods. Due to the coherent conversions between fluxon and localized modes, the ballistic gates can be very efficient: In our simulations, only a few percent of the fluxon's energy are dissipated in the gate operation. Ballistic-reversible gates can be combined with other nonballistic gate circuits to extend the range of gate functionalities. Here, we describe how the CNOT can be built as a structure that includes the Identity-else-Same-gives-NOT (IDSN) and store-and-launch (SNL) gates. The IDSN is a 2-b ballistic gate, which we describe and analyze in terms of equivalent 1-b circuits. The SNL is a clocking gate, which allows the storage of a bit and the clocked launch of a fluxon on a bit-state-dependent output path. In the CNOT, the SNL gates provide the necessary routing and fluxon synchronization for the input to the IDSN gate.